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32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT
Integrated Device Technology, Inc.
IDT49C460 IDT49C460A IDT49C460B IDT49C460C IDT49C460D IDT49C460E
FEATURES:
* Fast -- IDT49C460E -- IDT49C460D -- IDT49C460C -- IDT49C460B -- IDT49C460A -- IDT49C460 Low-power CMOS -- Commercial: 95mA (max.) -- Military: 125mA (max.) Improves system memory reliability -- Corrects all single bit errors, detects all double and some triple-bit errors Cascadable -- Data words up to 64-bits Built-in diagnostics -- Capable of verifying proper EDC operation via software control Simplified byte operations -- Fast byte writes possible with separate byte enables Functional replacement for 32- and 64-bit configurations of the AM29C60 and AM29C660 Available in PGA, PLCC and Fine Pitch Flatpack Military product compliant to MIL-STD-883, Class B Standard Military Drawing #5962-88533 Detect 10ns (max.) 12ns (max.) 16ns (max.) 25ns (max.) 30ns (max.) 40ns (max.) Correct 14ns (max.) 18ns (max.) 24ns (max.) 30ns (max.) 36ns (max.) 49ns (max.)
DESCRIPTION:
The IDT49C460s are high-speed, low-power, 32-bit Error Detection and Correction Units which generate check bits on a 32-bit data field according to a modified Hamming Code and correct the data word when check bits are supplied. The IDT49C460s are performance-enhanced functional replacements for 32-bit versions of the 2960. When performing a read operation from memory, the IDT49C460s will correct 100% of all single bit errors and will detect all double bit errors and some triple bit errors. The IDT49C460s are easily cascadable to 64-bits. Thirtytwo-bit systems use 7 check bits and 64-bit systems use 8 check bits. For both configurations, the error syndrome is made available. The IDT49C460s incorporate two built-in diagnostic modes. Both simplify testing by allowing for diagnostic data to be entered into the device and to execute system diagnostics functions. They are fabricated using a CMOS technology designed for high-performance and high-reliability. The devices are packaged in a 68-pin ceramic PGA, PLCC and Ceramic Quad Flatpack. Military grade product is manufactured in compliance with the latest revision of MIL-STD-883, Class B, making it ideally suited to military temperature applications demanding the highest level of performance and reliability.
*
*
* *
* * * * *
FUNCTIONAL BLOCK DIAGRAM
CB0-7 DATA0-31 8 DATA LATCH 4 8 32 32 DATA LATCH CHECK BIT GENERATE 8 MUX MUX CHECK BIT IN LATCH LEIN 13 MUX DIAGNOSTIC LATCH 8 5 CONTROL LOGIC 8 SC0-7 32 ERROR CORRECT ERROR DECODE 8 MUX
OE BYTE0-3
OESC
SYNDROME GENERATE
ERROR DETECT
ERROR MULT ERROR
LEDIAG LEOUT/GENERATE CORRECT CODE ID1,0 DIAG MODE1,0
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
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MILITARY AND COMMERCIAL TEMPERATURE RANGES
(c)1995 Integrated Device Technology, Inc.
AUGUST 1995
DSC-9017/8
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IDT49C460/A/B/C/D/E 32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT
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PIN CONFIGURATIONS
LEIN DIAG MODE1 DIAG MODE0 CODE ID1 CODE ID0
D31 D30 D29 D28 D27 D26 D25 GND
OE0
OE3
D1 D0
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
DESIGNATES PIN 1 FOR PLCC ONLY 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 D24 D23 D22 D21 D20 D19 D18 D17 VCC D16
VCC D2 D3 D4 D5 D6 D7 D8 GND D9 D10 D11 D12 D13 D14 D15
OE1
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
J68-1
OE2
LEOUT/GENERATE CORRECT LEDIAG
ERROR MULT ERROR
GND
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
PLCC TOPVIEW
11.6
OESC
CB7 CB6 CB5 CB4 CB3 CB2 CB1 CB0 SC0 SC1 SC2 SC3 SC4 SC5 SC6 SC7
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IDT49C460/A/B/C/D/E 32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT
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LEIN DIAG MODE1 DIAG MODE0 CODE ID1
CODE ID0
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 VCC D2 D3 D4 D5 D6 D7 D8 GND D9 D10 D11 D12 D13 D14 D15 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 D24 D23 D22 D21 D20 D19 D18 D17 VCC D16
PIN 1 IDENTIFICATION
F68 - 2
D31 D30 D29 D28 D27 D26 D25 GND
OE0
D1 D0
OE3
OE2
LEOUT/GENERATE CORRECT LEDIAG
OE1
ERROR MULT ERROR
GND
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
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FINE PITCH FLATPACK TOPVIEW
11.6
OESC
CB7 CB6 CB5 CB4 CB3 CB2 CB1 CB0 SC0 SC1 SC2 SC3 SC4 SC5 SC6 SC7
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IDT49C460/A/B/C/D/E 32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT
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LEOUT/GENERATE CORRECT LEDIAG
ERROR MULT ERROR
36 35 32 30 28
D24 GND D23 D22 D21 D20 D19 D18 D17 VCC D16
53 D25 D27 D26 D29 D28 D31 D30 CODE ID0
51 52 55 57 59 61 63 65 67 1 54 56 58 60 62 64 66
50 49
48 47
46 45
44 43
42 41
40 39
38 37
GND
34 OESC SC7 SC6 SC5 SC4 SC3 SC2 SC1 SC0 CB0 CB1 CB2 CB3 CB4 CB5 CB6 19 33 31 29 27 25 23 21
OE 2
OE3
G68 - 1
26 24 22 20
DIAG MODE0 CODE ID1 LEIN DIAG MODE1 D0 D1
OE 0
68
3 4
5 6
7 8
9 10
11 12
13 14
15 16
18 17
2
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VCC D2 D3 D4 D5 D6 D7 D8 GND D9 D10 D11 D12 D13 D14 D15 CB7
PGA TOPVIEW
11.6
OE 1
4
IDT49C460/A/B/C/D/E 32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT
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PIN DESCRIPTIONS
Pin Name DATA0-31 CB0-7 LEIN I/O I/O I I Description 32 bidirectional data lines provide input to the Data Input Latch and Diagnostic Latch and also receive output from the Data Output Latch. DATA0 is the LSB; DATA31 is the MSB. Eight check bit input lines input check bits for error detection and also used to input syndrome bits for error correction in 64-bit applications. Latch Enable is for the Data Input Latch. Controls latching of the input data. Data Input Latch and Check Bit Input Latch are latched to their previous state when LOW. When HIGH, the Data Input Latch and Check Bit Input Latch follow the input data and input check bits. A multifunction pin which, when LOW, is in the Check Bit Generate Mode. In this mode, the device generates the check bits or GENERATE partial check bits specific to the data in the Data Input Latch. The generated check bits are placed on the SC outputs. Also, when LOW, the Data Out Latch is latched to its previous state. When HIGH, the device is in the Detect or Correct Mode. In this mode, the device detects single and multiple errors and generates syndrome bits based upon the contents of the Data Input Latch and Check Bit Input Latch. In the Correct Mode, single bit errors are also automatically corrected and the corrected data is placed at the inputs of the Data Output Latch. The syndrome result is placed on the SC outputs and indicates in a coded form the number of errors and the specific bit-in-error. When HIGH, the Data Output Latch follows the output of the Data Input Latch as modified by the correction logic network. In Correct Mode, single bit errors are corrected by the network before being loaded into the Data Output Latch. In Detect Mode, the contents of the Data Input Latch are passed through the correction network unchanged into the Data Output Latch. The Data Output Latch is disabled, with its contents unchanged, if the EDC is in the Generate Mode. SC0-7 O Syndrome Check Bit outputs. Eight outputs which hold the check bits and partial check bits when the EDC is in the Generate Mode and will hold the syndrome/partial syndrome bits when the device is in the Detect or Correct modes. All are 3-state outputs. Output Enable--Syndrome Check Bits. In the HIGH condition, the SC outputs are in the high impedance state. When LOW, all SC output lines are enabled. In the Detect or Correct Mode, this output will go LOW if one or more data or check bits contain an error. When HIGH, no errors have been detected. This pin is forced HIGH in the Generate Mode. In the Detect or Correct Mode, this output will go LOW if two or more bit errors have been detected. A HIGH level indicates that either one or no errors have been detected. This pin is forced HIGH in the Generate Mode. The correct input which, when HIGH, allows the correction network to correct any single-bit error in the Data Input Latch (by complementing the bit-in-error) before putting it into the Data Output Latch. When LOW, the device will drive data directly from the Data Input Latch to the Data Output Latch without correction. Output Enable--Bytes 0, 1, 2, 3. Data Output Latch. Control the three-state output buffers for each of the four bytes of the Data Output Latch. When LOW, they enable the output buffer of the Data Output Latch. When HIGH, they force the Data Output Latch buffer into the high impedance mode. One byte of the Data Output Latch is easily activated by separately selecting the four enable lines. Select the proper diagnostic mode. They control the initialization, diagnostic and normal operation of the EDC. These two code identification inputs identify the size of the total data word to be processed. The two allowable data word sizes are 32 and 64 bits and their respective modified Hamming Codes are designated 32/39 and 64/72. Special CODE ID1,0, input 01 is also used to instruct the EDC that the signals CODE ID1,0, DIAG MODE1,0 and CORRECT are to be taken from the Diagnostic Latch rather than from the input control lines. This is the Latch Enable for the Diagnostic Latch. When HIGH, the Diagnostic Latch follows the 32-bit data on the input lines. When LOW, the outputs of the Diagnostic Latch are latched to their previous states. The Diagnostic Latch holds diagnostic check bits and internal control signals for CODE ID1,0, DIAG MODE1,0 and CORRECT.
2584 tbl 01
LEOUT/
GENERATE
OESC ERROR MULT ERROR
CORRECT
I O O I
OE BYTE0-3
I
DIAG MODE1,0 CODE ID1,0
I I
LEDIAG
I
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IDT49C460/A/B/C/D/E 32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT
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EDC ARCHITECTURE SUMMARY
The IDT49C460s are high-performance cascadable EDCs used for check bit generation, error detection, error correction and diagnostics. The function blocks for this 32-bit device consist of the following: * Data Input Latch * Check Bit Input Latch * * * * Check Bit Generation Logic Syndrome Generation Logic Error Detection Logic Error Correction Logic
ERROR DETECTION LOGIC
This part of the device decodes the syndrome bits generated by the Syndrome Generation Logic. With no errors in either the input data or check bits, both the ERROR and MULTERROR outputs are HIGH. ERROR will go low if one error is detected. MULTERROR and ERROR will both go low if two or more errors are detected.
ERROR CORRECTION LOGIC
In single error cases, this logic complements (corrects) the single data bit-in-error. This corrected data is loaded into the Data Output Latch, which can then be read onto the bidirectional data lines. If the error is resulting from one of the check bits, the correction logic does not place corrected check bits on the syndrome/check bit outputs. If the corrected check bits are needed, the EDC must be switched to the Generate Mode.
* Data Output Latch * Diagnostic Latch * Control Logic
DATA INPUT/OUTPUT LATCH
The Latch Enable Input, LEIN, controls the loading of 32 bits of data to the Data In Latch. The data from the DATA lines can be loaded in the Diagnostic Latch under control of the Diagnostic Latch Enable, LEDIAG, giving check bit information in one byte and control information in another byte. The Diagnostic Latch is used in the Internal Control Mode or in one of the diagnostic modes. The Data Output Latch has buffers that place data on the DATA lines. These buffers are split into four 8-bit buffers, each having their own output enable controls. This feature facilitates byte read and byte modify operations.
DATA OUTPUT LATCH AND OUTPUT BUFFERS
The Data Output Latch is used for storing the result of an error correction operation. The latch is loaded from the correction logic under control of the Data Output Latch Enable, LEOUT. The Data Output Latch may also be directly loaded from the Data Input Latch in the PASSTHRU mode. The Data Output Latch buffer is split into 4 individual buffers which can be enabled by OE0-3 separately for reading onto the bidirectional data lines.
DIAGNOSTIC LATCH
The diagnostic latch is loadable under control of the Diagnostic Latch Enable, LEDIAG, from the bidirectional data lines. Check bit information is contained in one byte while the other byte contains the control information. The Diagnostic Latch is used for driving the device when in the Internal Control Mode, or for supplying check bits when in one of the diagnostic modes.
CHECK BIT GENERATION LOGIC
This generates the appropriate check bits for the 32 bits of data in the Data Input Latch. The modified Hamming Code is the basis for generating the proper check bits.
SYNDROME GENERATION LOGIC
In both the Detect and Correct modes, this logic does a comparison on the check bits read from memory against the newly generated set of check bits produced for the data read in from memory. Matching sets of check bits mean no error was detected. If there is a mismatch, one or more of the data or check bits is in error. Syndrome bits are produced by an exclusive-OR of the two sets of check bits. Identical sets of check bits mean the syndrome bits will be all zeros. If an error results, the syndrome bits can be decoded to determine the number of errors and the specific bit-in-error.
CONTROL LOGIC
Specifies in which mode the device will be operating in. Normal operation is when the control logic is driven by external control inputs. In the Internal Control Mode, the control signals are read from the Diagnostic Latch. Since LEOUT and GENERATE are controlled by the same pin, the latching action (LEOUT from high to low) of the Data Output Latch causes the EDC to go into the Generate Mode.
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IDT49C460/A/B/C/D/E 32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT
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DETAILED PRODUCT DESCRIPTION
The IDT49C460 EDC units contain the logic necessary to generate check bits on 32 bits of data input according to a modified Hamming Code. The EDC can compare internally generated check bits against those read with the 32-bit data to allow correction of any single bit data error and detection of all double (and some triple) bit errors. The IDT49C460s can be used for 32-bit data words (7 check bits) and 64-bit (8 check bits) data words.
Correct X X
Diag Diag Mode0 Mode1 0 0 0 1
Diagnostic Mode Selected Non-diagnostic Mode. Normal EDC function in this mode. Diagnostic Generate. The con tents of the Diagnostic Latch are substituted for the normally generated check bits when in the Generate Mode. The EDC functions normally in the Detect or Correct modes. Diagnostic Detect/Correct. In either mode, the contents of the Diagnostic Latch are substituted for the check bits normally read from the Check Bit Input Latch. The EDC functions normally in the Generate Mode. Initialize. The Data Input Latch outputs are forced to zeros and latched upon removal of Initialize Mode. PASSTHRU.
2584 tbl 02
WORD SIZE SELECTION
The two code identification pins, CODE ID1, 0, are used to determine the data word size that is 32 or 64 bits. They also select the Internal Control Mode. Table 4 defines all possible slice identification codes.
0/1 1 0
CHECK AND SYNDROME BITS
The IDT49C460s provide either check bits or syndrome bits on the three-state output pins, SC0-7. Check bits are generated from a combination of the Data Input bits, while syndrome bits are an exclusive-OR of the check bits generated from read data with the read check bits stored with the data. Syndrome bits can be decoded to determine the single bit in error or that a double (some triple) error was detected. The check bits are labeled: C0, C1, C2, C3, C4, C5, C6 C0, C1, C2, C3, C4, C5, C6, C7 for the 32-bit configuration for the 64-bit configuration
1 1 1
0
1
1
Table 2. Diagnostic Mode Control
Syndrome bits are similarly labeled S0 through S7.
Operating Mode Generate Detect Correct PASSTHRU Diagnostic Generate Diagnostic Detect Diagnostic Correct Initialization Internal SC0-7 (OE = LOW) OESC Check Bits Generated from DATAIN Latch Syndrome Bits DATAIN/ Check Bit Latch Syndrome Bits DATAIN/ Check Bit Latch Check Bit Latch Check Bits from Diagnostic Latch Syndrome Bits DATAIN/ Diagnostic Latch Syndrome Bits DATAIN/ Diagnostic Latch --
DM0 0 1 0 0 0 0 1 0 1 1 1
DM1 0 0 0 1 0 1 1 1 0 0 1
Generate 0 1 1 1 0 1 1 1
Correct X 0 1 0 X 0 1 1
DATAOUT Latch LEOUT = LOW (1) DATAIN Latch DATAIN Latch w/ Single Bit Correction DATAIN Latch -- DATAIN Latch DATAIN Latch w/ Single Bit Correction DATAIN Latch Set to 0000(3)
ERROR MULT ERROR
High Error Dep (2) Error Dep High High Error Dep Error Dep --
CODE ID1,0 = 01 (Control Signals CODE ID1,0, DIAG MODE1,0 and CORRECT are taken from Diagnostic Latch.)
2584 tbl 03 NOTES: 1. In Generate Mode, data is read into the EDC unit and the check bits are generated. The same data is written to memory along with the check bits. Since the DATAOUT Latch is not used in the Generate Mode, LEOUT (being LOW since it is tied to Generate) does not affect the writing of check bits. 2. Error Dep (Error Dependent): ERROR will be low for single or multiple errors, with MULT ERROR low for double or multiple errors. Both signals are high for no errors. 3. LEIN is LOW.
Table 3. IDT49C460 Operating Modes
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IDT49C460/A/B/C/D/E 32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT
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OPERATING MODE SELECTION
Tables 2 and 3 describe the nine operating modes of the IDT49C460s. The Diagnostic Mode pins -- DIAG MODE0,1 -- define four basic areas of operation. GENERATE and CORRECT further divide operation into 8 functions, with CODE ID1,0 defining the ninth mode as the Internal Mode. Generate Mode is used to display the check bits on the outputs SC0-7. The Diagnostic Generate Mode displays check bits as stored in the Diagnostic Latch. Detect Mode provides an indication of errors or multiple errors on the outputs ERROR and MULT ERROR. Single bit errors are not corrected in this mode. The syndrome bits are provided on the outputs SC0-7. For the Diagnostic Detect Mode, the syndrome bits are generated by comparing the internally generated check bits from the Data In Latch with
Code ID1 0 0 1 1 Code ID0 0 1 0 1 Slice Selected 32-Bit Internal Control Mode 64-Bit, Lower 32-Bit (0-31) 64-Bit, Upper 32-Bit (32-63)
2584 tbl 04
check bits stored in the diagnostic latch rather than with the check bit latch contents. Correct Mode is similar to the Detect Mode except that single bit errors will be complemented (corrected) and made available as input to the Data Out Latches. Again, the Diagnostic Correct Mode will correct single bit errors as determined by syndrome bits generated from the data input and contents of the diagnostic latches. The Initialize Mode provides check bits for all zero bit data. Data Input Latches are set, latched to a logic zero and made available as input to the Data Out Latches. The Internal Mode disables the external control pins DIAG MODE0,1 and CORRECT to be defined by the Diagnostic Latch. Even CODE ID1,0, although externally set to the 01 code, can be redefined from the Diagnostic Latch data.
CHECK-BIT INPUTS DATA INPUT DATA32-63 DATA0-31 32 DATA 8 CB0-7 1/8 IDT74FCT240
OESC
Table 4. Slice Identification
OESC
DATA0-31 HIGH
C6
C5
C4
C3
C2
C1
C0
32
IDT49C460 (LOWER 32 BITS) SC0-7 CODE ID1,0 8 DATA CB0-7 1,0
DATA0-31
CB7
CB6 CB5 CB4 CB3 CB2 CB1 CB0
IDT49C460
CODE ID1,0
0,0
OESC
IDT49C460 (UPPER 32 BITS)
SC7
SC6
SC5
SC4
SC3
SC2
SC1
SC0
MULT ERROR ERROR MULT ERROR
CODE ID1,0 SC0-7 8
1,1
NC S6/C6
S5/C5 S4/C4
S3/C3 S2/C2
S1/C1 S0/C0
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ERROR
Figure 1. 32-Bit Configuration
SYNDROME/ CHECK BITS
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Figure 2. 64-Bit Configuration
DATA BYTE3 31 BYTE2 BYTE1 BYTE0 0 C0 C1 24 23 16 15 87
CHECK BITS C2 C3 C4 C5 C6
Figure 3. 32-Bit Data Format
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DATA BYTE7 63 BYTE6 BYTE5 BYTE4 BYTE3 BYTE2 BYTE1 BYTE0 0 C0 C1 C2 56 55 48 47 40 39 32 31 24 23 16 15 87
CHECK BITS C3 C4 C5 C6 C7
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Figure 4. 64-Bit Data Format
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IDT49C460/A/B/C/D/E 32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT
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32-BIT DATA WORD CONFIGURATION
A single IDT49C460 EDC unit, connected as shown in Figure 1, provides all the logic needed for single bit error correction and double bit error detection of a 32-bit data field. The identification code indicates 7 check bits are required. The CB7 pin should be HIGH. Figure 3 indicates the 39-bit data format for two bytes of data and 7 check bits. Table 3 describes the operating mode available. Table 6 indicates the data bits participating in the check bit generation. For example, check bit C0 is the exclusive-OR function of the 16 data input bits marked with an X. Check bits are generated and output in the Generate and Initialization Mode. Check bits from the respective latch are passed, unchanged, in the PASSTHRU or Diagnostic Generate Mode. Syndrome bits are generated by an exclusive-OR or the
BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8 BIT 9 BIT 10 BIT 11 BIT 12 BIT 13-31
generated check bits with the read check bits. For example, Sn is the XOR of check bits Cn from those read with those generated. Table 7 indicates the decoding of the seven syndrome bits to identify the bit-in-error for a single bit error, or whether a double or triple bit error was detected. The all zero case indicates no errors detected. In the Correct Mode, the syndrome bits are used to complement (correct) single bit errors in the data bits. For double or multiple error detection, the data available as input to the Data Out Latch is not defined. Table 5 defines the bit definition for the Diagnostic Latch. As defined in Table 3, several modes will use the diagnostic check bits to determine syndrome bits or to pass as check bits to the SC0-7 outputs. The Internal Mode substitutes the indicated bit position for the external control signals.
CB0 DIAGNOSTIC CB1 DIAGNOSTIC CB2 DIAGNOSTIC CB3 DIAGNOSTIC CB4 DIAGNOSTIC CB5 DIAGNOSTIC CB6 DIAGNOSTIC CB7 DIAGNOSTIC CODE ID0 CODE ID1 DIAG MODE0 DIAG MODE1 CORRECT DON'T CARE
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Table 5. 32-Bit Diagnostic Latch Coding Format
Generated Check Bits C0 C1 C2 C3 C4 C5 C6
Participating Data Bits Parity Even (XOR) Even (XOR) Odd (XNOR) Odd (XNOR) Even (XOR) Even (XOR) Even (XOR) X X X X X X X X
2584 tbl 06
0 X X X X
1 X X
2 X
3
4 X X
5
6 X X
7 X X
8 X X
9 X
10 X
11 X
12 X
13
14 X
15
X X X
X X X X X X
X
X X X X
X X X
X X X
X X X X X
X
X
X
Generated Check Bits C0 C1 C2 C3 C4 C5 C6
Participating Data Bits Parity Even (XOR) Even (XOR) Odd (XNOR) Odd (XNOR) Even (XOR) Even (XOR) Even (XOR) X X X X X X X 16 17 X X 18 X X X 19 X X X X X X X 20 21 X X X X X X X X X X X X X X X X X X X 22 23 24 25 26 X X X X X 27 28 X X X X X X X X X X
2584 tbl 07
29 X
30
31 X X
Table 6. 32-Bit Modified Hamming Code-Check Bit Encode Chart 11.6 9
IDT49C460/A/B/C/D/E 32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT
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Syndrome Bits Hex S3 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 S2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 S1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 S0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Hex 0 S6 0 S5 S4 0 0 * C0 C1 T C2 T T M C3 T T 17 T M 16 T
1 0 0 1
2 0 1 0
3 0 1 1 T 14 M T 15 T T M M T T M T M M T
4 1 0 0 C6 T T M T M M T T M 1 T M T T 0
5 1 0 1 T M 2 T 3 T T 4 5 T T 6 T 7 M T
6 1 1 0 T M 24 T 25 T T 26 27 T T 28 T 29 M T
7 1 1 1 30 T T M T 31 M T T M M T M T T M
C4 C5 T T 18 T 19 20 T T 21 22 T 23 T T M T T 8 T 9 10 T T 11 12 T 13 T T M
NOTES: 1. * = No errors detected 2. Number = The number of the single bit-in-error 3. T = Two errors detected 4. M = Three or more errors detected Table 7. Syndrome Decode to Bit-in-Error (32-Bit)
2584 tbl 08
Table 3 describes the operating modes available for the 64/ 72 configuration. Table 11 indicates the data bits participating in the check bit generation. For example, check bit C0 is the exclusive-OR function of the 32 data input bits marked with an X. Check bits are generated and output in the Generate and Initialization modes. Check bits are passed as stored in the PASSTHRU or Diagnostic Generate modes. Syndrome bits are generated by an exclusive-OR of the generated check bits with the read check bits. For example, Sn is the XOR of check bits Cn from those read with those generated. Table 9 indicates the decoding of the 8 syndrome bits to determine the bit in error for a single bit error or whether a double or triple bit error was detected. The all zero case indicates no errors detected. In the Correct Mode, the syndrome bits are used to complement (correct) single bit errors in the data bits. For double or multiple error detection, the data available as input to the Data Out Latch is not defined. Tables 8A and 8B define the bit definition for the Diagnostic Latch. As defined in Table 3, several modes will use the Diagnostic Check Bits to determine syndrome bits or to pass as check bits to the SC0-7 outputs. The Internal Mode substitutes the indicated bit position for the external control signals. Performance data is provided in Table 10, relating a single IDT49C460 EDC with the two cascaded units of Figure 2. As indicated, a summation of propagation delays is required from the cascading arrangement of EDC units.
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13-31 32-39 40 41 42 43 44 45-63 Internal Function CB0 DIAGNOSTIC CB1 DIAGNOSTIC CB2 DIAGNOSTIC CB3 DIAGNOSTIC CB4 DIAGNOSTIC CB5 DIAGNOSTIC CB6 DIAGNOSTIC CB7 DIAGNOSTIC CODE ID0 LOWER 32-BIT CODE ID1 LOWER 32-BIT DIAG MODE0 LOWER 32-BIT DIAG MODE1 LOWER 32-BIT CORRECT LOWER 32-BIT DON'T CARE DON'T CARE CODE ID0 UPPER 32-BIT CODE ID1 UPPER 32-BIT DIAG MODE0 UPPER 32-BIT DIAG MODE1 UPPER 32-BIT CORRECT UPPER 32-BIT DON'T CARE
2584 tbl 09
64-BIT DATA WORD CONFIGURATION
Two IDT49C460 EDC units, connected as shown in Figure 2, provide all the logic needed for single bit error detection and double bit error detection of a 64-bit data field. Table 4 gives the CODE ID1,0 values needed for distinguishing the upper 32 bits from the lower 32 bits. Valid syndrome, check bits and the ERROR and MULT ERROR signals come from the IC with the CODE ID1,0 = 11. Control signals not indicated are connected to both units in parallel. The EDC with the CODE ID1,0 = 10 has the OESC grounded. The OESC selects the syndrome bits from the EDC with CODE ID1,0 = 11 and also controls the check bit buffers from memory. Data In bits 0 through 31 are connected to the same numbered inputs of the EDC unit with CODE ID1,0 = 10, while Data In bits 32 through 63 are connected to Data Inputs 0 to 31, respectively, for the EDC unit with CODE ID1,0 = 11. Figure 4 indicates the 72-bit data format of 8 bytes of data and 8 check bits. Check bits are input to the EDC unit with CODE ID1,0 = 10 through a three-state buffer unit such as the IDT74FCT244. Correction of single bit errors of the 64-bit configuration requires a feedback of syndrome bits from the upper EDC unit to the lower EDC unit. The MUX shown on the functional block diagram is used to select the CB0-7 pins as the syndrome bits rather than internally generated syndrome bits.
Table 8A. 64-Bit Diagnostic Latch-Coding Format (Diagnostic and Correct Mode) 10
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IDT49C460/A/B/C/D/E 32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Bit 0-7 8 9 10 11 12 13-31 32 33 34 35 36 37 38 39 40 41 42 43 44 45-63
Internal Function DON'T CARE CODE ID0 LOWER 32-BIT CODE ID1 LOWER 32-BIT DIAG MODE0 LOWER 32-BIT DIAG MODE1 LOWER 32-BIT CORRECT LOWER 32-BIT DON'T CARE CB0 DIAGNOSTIC CB1 DIAGNOSTIC CB2 DIAGNOSTIC CB3 DIAGNOSTIC CB4 DIAGNOSTIC CB5 DIAGNOSTIC CB6 DIAGNOSTIC CB7 DIAGNOSTIC CODE ID0 UPPER 32-BIT CODE ID1 UPPER 32-BIT DIAG MODE0 UPPER 32-BIT DIAG MODE1 UPPER 32-BIT CORRECT UPPER 32-BIT DON'T CARE
2584 tbl 10
Table 8B. 64-Bit Diagnostic Latch-Coding Format (Diagnostic and Correct Mode)
Hex Syndrome Bits Hex 0 1 2 3 4 5 6 7 8 9 A B C D E F S3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 S2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 S1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 S0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 S7 S6 S5 S4
0 0 0 0 0 * C0 C1 T C2 T T M C3 T T 17 T M 16 T
1 0 0 0 1 C4 T T 18 T 19 20 T T 21 22 T 23 T T M
2 0 0 1 0 C5 T T 8 T 9 10 T T 11 12 T 13 T T M
3 0 0 1 1 T 14 M T 15 T T M M T T M T M M T
4 0 1 0 0 C6 T T M T M M T T M 33 T M T T 32
5 0 1 0 1 T M 34 T 35 T T 36 37 T T 38 T 39 M T
6 0 1 1 0 T M 56 T 57 T T 58 59 T T 60 T 61 M T
7 0 1 1 1 62 T T M T 63 M T T M M T M T T M
8 1 0 0 0 C7 T T M T M M T T M 49 T M T T 48
9 1 0 0 1 T M 50 T 51 T T 52 53 T T 54 T 55 M T
A 1 0 1 0 T M 40 T 41 T T 42 43 T T 44 T 45 M T
B 1 0 1 1 46 T T M T 47 M T T M M T M T T M
C 1 1 0 0 T M M T M T T M M T T 1 T M 0 T
D 1 1 0 1 M T T 2 T 3 4 T T 5 6 T 7 T T M
E 1 1 1 0 M T T 24 T 25 26 T T 27 28 T 29 T T M
F 1 1 1 1 T 30 M T 31 T T M M T T M T M M T
2584 tbl 11
NOTES: * = No errors detected Number = The number of the single bit-in-error
T = Two errors detected M = Three or more errors detected
Table 9. Syndrome Decode to Bit-In-Error (64-Bit Configuration)
11.6
11
IDT49C460/A/B/C/D/E 32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
64-Bit Propagation Delay From DATA DATA DATA DATA DATA To Check Bits Out Corrected DATAOUT Syndromes Out Component Delay for IDT49C460 AC Specifications (DATA TO SC) + (CB TO SC, CODE ID 11) (DATA TO SC) + (CB TO SC, CODE ID 11) + (CB TO DATA, CODE ID 10) (DATA TO SC) + (CB TO SC, CODE ID 11) (DATA TO SC) + (CB TO ERROR, CODE ID 11) (DATA TO SC) + (CB TO MULT ERROR, CODE ID 11)
2584 tbl 12
ERROR for 64 Bits MULT ERROR for 64 Bits
Table 10. Key Calculations for the 64-Bit Configuration
11.6
12
IDT49C460/A/B/C/D/E 32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Generated Check Bits C0 C1 C2 C3 C4 C5 C6 C7
Participating Data Bits Parity Even (XOR) Even (XOR) Odd (XNOR) Odd (XNOR) Even (XOR) Even (XOR) Even (XOR) Even (XOR) X X X X X X X X X X X X X X X X
2584 tbl 13
0 X X X
1 X X X
2 X X
3 X
4 X
5 X
6 X
7
8 X X
9 X
10 X
11 X
12 X
13
14 X
15
X X X
X X X X X X
X X X X
X
X X X X
X X X
X X X
X
X
X
X
X
Generated Check Bits C0 C1 C2 C3 C4 C5 C6 C7
Participating Data Bits Parity Even (XOR) Even (XOR) Odd (XNOR) Odd (XNOR) Even (XOR) Even (XOR) Even (XOR) Even (XOR) X X X X X X X 16 17 X X 18 X X X 19 X X X X X X X 20 21 X X X X X X X X X X X X X X X X X X X X X X X 22 23 24 X X X 25 X X X X X 26 27 X X X X X X X X X X X X
2584 tbl 14
28
29
30 X
31
X
Generated Check Bits C0 C1 C2 C3 C4 C5 C6 C7
Participating Data Bits Parity Even (XOR) Even (XOR) Odd (XNOR) Odd (XNOR) Even (XOR) Even (XOR) Even (XOR) Even (XOR) X X X X X X X X X X X X X X X X
2584 tbl 15
32 X X X X
33 X X
34 X
35
36 X X
37
38 X X
39 X
40 X
41
42 X X
43
44 X X
45 X X
46
47 X X
X X X
X X X X X X
X X X X
X
X X X X
X X X X X X
X
X
X
Generated Check Bits C0 C1 C2 C3 C4 C5 C6 C7 Parity Even (XOR) Even (XOR) Odd (XNOR) Odd (XNOR) Even (XOR) Even (XOR) Even (XOR) Even (XOR) X X X X X X 48 X X X X X X X X X X X 49 50 51 52 X X X X X 53
Participating Data Bits 54 X X X X X X X X X X X
2584 tbl 16
55 X
56 X
57
58 X X
59
60 X X
61 X X
62
63 X X
X
X X X X X
X X X X X X X X X
X X
X X
X X
NOTE: 1. The check bit is generated as either an XOR or XNOR of the 32 data bits noted by an "X" in the table. Table 11. 64-Bit Modified Hamming Code-Check Bit Encoding
11.6
13
IDT49C460/A/B/C/D/E 32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SC OUTPUTS
The tables below indicate how the SC0-7 outputs are generated in each control mode of various CODE IDs (Internal Control Mode not applicable).
CODE ID1,0 Generate SC0 SC1 SC2 SC3 SC4 SC5 SC6 SC7 00 PH0 PA PB PC PD PE PF -- Final Check Bits 10 PH1 PA PB PC PD PE PF PF Partial Check Bits 11 PH2 CB0 PA CB1 PB CB2 PC CB3 PD CB4 PE CB5 PF CB6 PG CB7 Final Check Bits
2584 tbl 17
Correct/ Detect SC0 SC1 SC2 SC3 SC4 SC5 SC6 SC7 00 PH0 C0 PA C1 PB C2 PC C3 PD C4 PE C5 PF C6 -- Final Syndrome
CODE ID1,0 10 PH1 C0 PA C1 PB C2 PC C3 PD C4 PE C5 PF C6 PF C7 Partial Syndrome 11 PH2 CB0 PA CB1 PB CB2 PC CB3 PD CB4 PE CB5 PF CB6 PG CB7 Final Syndrome
2584 tbl 19
Diagnostic Generate SC0 SC1 SC2 SC3 SC4 SC5 SC6 SC7 00 DL0 DL1 DL2 DL3 DL4 DL5 DL6 -- Final Check Bits
CODE ID1,0 10 DL0 DL1 DL2 DL3 DL4 DL5 DL6 DL7 Partial Check Bits 11 DL32 DL33 DL34 DL35 DL36 DL37 DL38 DL39 Final Check Bits
2584 tbl 18
Diagnostic Correct/ Detect SC0 SC1 SC2 SC3 SC4 SC5 SC6 SC7
CODE ID1,0 00 PH0 DL0 PA DL1 PB DL2 PC DL3 PD DL4 PE DL5 PF DL6 -- Final Syndrome 10 PH1 DL0 PA DL1 PB DL2 PC DL3 PD DL4 PE DL5 PF DL6 PF DL7 Partial Syndrome 11 PH2 CB0 PA CB1 PB CB2 PC CB3 PD CB4 PE CB5 PF CB6 PG CB7 Final Syndrome
2584 tbl 20
CODE ID1,0 PASSTHRU SC0 SC1 SC2 SC3 SC4 SC5 SC6 SC7 00 C0 C1 C2 C3 C4 C5 C6 -- 10 C0 C1 C2 C3 C4 C5 C6 C7 11 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7
2584 tbl 21
Table 12. SC0-7 Outputs For Different Control Modes
11.6
14
IDT49C460/A/B/C/D/E 32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DATA CORRECTION
The tables below indicate which data output bits are corrected depending upon the syndromes and the CODE ID1,0 position. The syndromes that determine data correction are, in some cases, syndromes input externally via the CB inputs and, in some cases, syndromes input externally by that EDC (Si are the internal syndromes and are the same as the value of the SCi output of that EDC if enabled).
FUNCTIONAL EQUATIONS
The equations below describe the IDT49C460 output values as defined by the value of the inputs and internal states.
DEFINITIONS
PA = D0 D1 D2 D4 D6 D8 D10 D12 D16 D17 D18 D20 D22 D24 D26 D28 PB = D0 D3 D4 D7 D9 D10 D13 D15 D16 D19 D20 D23 D25 D26 D29 D31 PC = D0 D1 D5 D6 D7 D11 D12 D13 D16 D17 D21 D22 D23 D27 D28 D29 PD = D2 D3 D4 D5 D6 D7 D14 D15 D18 D19 D20 D21 D22 D23 D30 D31 PE = D8 D9 D10 D11 D12 D13 D14 D15 D24 D25 D26 D27 D28 D29 D30 D31 PF = D0 D1 D2 D3 D4 D5 D6 D7 D24 D25 D26 D27 D28 D29 D30 D31 PG = D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 PH0 = D0 D4 D6 D7 D8 D9 D11 D14 D17 D18 D19 D21 D26 D28 D29 D31 PH1 = D1 D2 D3 D5 D8 D9 D11 D14 D17 D18 D19 D21 D24 D25 D27 D30 PH2 = D0 D4 D6 D7 D10 D12 D13 D15 D16 D20 D22 D23 D26 D28 D29 D31
11.6
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IDT49C460/A/B/C/D/E 32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VTERM Rating Terminal Voltage with Respect to GND Power Supply Voltage Operating Temperature Temperature Under Bias Storage Temperature DC Output Current Com'l. -0.5 to VCC + 0.5V -0.5 to +7.0 0 to +70 -55 to +125 -55 to +125 30 Mil. -0.5 to VCC + 0.5V -0.5 to +7.0 -55 to +125 -65 to +135 -65 to +150 30 Unit V
CAPACITANCE (TA = + 25C, f = 1.0MHz)
Symbol CIN COUT Parameter
(1)
Conditions VIN = 0V VOUT = 0V
Typ. 5 7
Unit pF pF
2584 tbl 25
Input Capacitance Output Capacitance
VCC TA TBIAS TSTG IOUT
V
NOTE: 1. This parameter is sampled and not 100% tested.
C C C
mA
NOTE: 2584 tbl 24 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: VLC = 0.2V; VHC = VCC - 0.2V Commercial: TA = 0C to +70C, VCC = 5.0V 5%; Military: TA = -55C to +125C, VCC = 5.0V 10%
Symbol VIH VIL II H II L VOH Parameter Input HIGH Level Input LOW Level Input HIGH Current Input LOW Current Output HIGH Voltage Test Conditions (1) Guaranteed Logic HIGH Level (4) Guaranteed Logic LOW VCC = Max., VIN = VCC VCC = Max., VIN = GND VCC = Min. IOH = 300A IOH = -12mA Mil. IOH = -15mA Com'l. VOL Output LOW Voltage VCC = Min. IOL = 300A IOL = 12mA Mil. IOL = 16mA Com'l. IOZ IOS Off State (High Impedance) Output Current Output Short Circuit Current VCC = Max., VOUT = 0V (3) VCC = Max. VO = 0V VO = VCC (Max.) Level (4) Min. 2.0 -- -- -- VCC 2.4 2.4 -- -- -- -- -- -30.0 Typ. (2) -- -- 0.1 -0.1 -- 4.3 4.3 -- 0.3 0.3 -0.1 0.1 -- Max. -- 0.8 10.0 -10.0 -- -- -- GND 0.5 0.5 -20.0 20.0 -- mA
2584 tbl 26
Unit V V A A V
V
A
NOTES: 1. For conditions shown as Max. or Min. use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, + 25C ambient and maximum loading. 3. Not more than one output should be shorted at one time. Duration of the circuit test should not exceed one second. 4. These input levels provide zero noise immunity and should only be static tested in a noise-free environment.
11.6
16
IDT49C460/A/B/C/D/E 32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS (Cont'd.)
Commercial: TA = 0C to +70C, VCC = 5.0V 5%; Military: TA = -55C to +125C, VCC = 5.0V 10% VLC = 0.2V; VHC = VCC - 0.2V
Symbol ICCQ Parameter Quiescent Power Supply Current (CMOS Inputs) ICCT ICCD Quiescent Input Power Supply Current (per Input @ TTL High) Dynamic Power Supply Current
(5)
Test Conditions VCC = Max.; All Inputs VHC VIN, VIN VLC fOP = 0; Outputs Disabled VCC = Max., VIN = 3.4V, fOP = 0 VCC = Max. VHC VIN, VIN VLC Outputs Open, OE = L MIL. COM'L. MIL. COM'L.
Min. --
Typ. 3.0
Max. 10
Unit mA
-- -- -- -- --
0.3 6 6 60 60
0.75 10 7 110 80
mA/ Input mA/ MHz mA
ICC
Total Power Supply Current (6)
VCC = Max., fOP = 10MHz Outputs Open, OE = L 50 % Duty cycle VHC VIN, VIN VLC VCC = Max., fOP = 10MHz Outputs Open, OE = L 50 % Duty cycle VIH = 3.4V, VIL = 0.4V
MIL. COM'L.
-- --
70 70
125 95
NOTES: 2584 tbl 27 5. ICCT is derived by measuring the total current with all the inputs tied together at 3.4V, subtracting out ICCQ, then dividing by the total number of inputs. 6. Total Supply Current is the sum of the Quiescent current and the Dynamic current (at either CMOS or TTL input levels). For all conditions, the Total Supply Current can be calculated by using the following equation: ICC = ICCQ + ICCT (NT x DH) + ICCD (fOP) DH = Data duty cycle TTL high period (VIN = 3.4V). NT = Number of dynamic inputs driven at TTL levels. fOP = Operating frequency in Megahertz.
CMOS TESTING CONSIDERATIONS
Special test board considerations must be taken into account when applying high-speed CMOS products to the automatic test environment. Large output currents are being switched in very short periods and proper testing demands that test set-ups have minimized inductance and guaranteed zero voltage grounds. The techniques listed below will assist the user in obtaining accurate testing results: 1) All input pins should be connected to a voltage potential during testing. If left floating, the device may oscillate, causing improper device operation and possible latchup. 2) Placement and value of decoupling capacitors is critical. Each physical set-up has different electrical characteristics and it is recommended that various decoupling capacitor sizes be experimented with. Capacitors should be positioned using the minimum lead lengths. They should also be distributed to decouple power supply lines and be placed as close as possible to the DUT power pins.
3) Device grounding is extremely critical for proper device testing. The use of multi-layer performance boards with radial decoupling between power and ground planes is necessary. The ground plane must be sustained from the performance board to the DUT interface board and wiring unused interconnect pins to the ground plane is recommended. Heavy gauge stranded wire should be used for power wiring, with twisted pairs being recommended for minimized inductance. 4) To guarantee data sheet compliance, the input thresholds should be tested per input pin in a static environment. To allow for testing and hardware-induced noise, IDT recommends using VIL 0V and VIH 3V for AC tests.
11.6
17
IDT49C460/A/B/C/D/E 32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT49C460E AC ELECTRICAL CHARACTERISTICS
(Guaranteed Commercial Range Performance) Temperature range: 0C to +70C, VCC = 5.0V 5% The inputs switch between 0V to 3V with signal measured at the 1.5V level.
PROPAGATION DELAYS(1)
To Output From Input DATA0-31 (3) CB0-7 (CODE ID = 00, 11) 1,0 CB0-7 (CODE ID = 10) 1,0 LEOUT/GENERATE CORRECT Not Internal Control Mode DIAG MODE Not Internal Control Mode CODE ID1,0 LEIN From latched to Transparent LEDIAG From latched to Transparent Internal Control Mode LEDIAG (Internal Control Mode) From latched to Transparent DATA0-31 (Internal Control Mode) Via Diagnostic Latch SC 0-7 11 9 9 -- 13 -- 11 13(6) 16 DATA 0-31 14(2) 12 10 9 -- 11 18 17 19 17 16
ERROR
10 7 --
MULT ERROR
11 9 -- 8 8
Unit ns ns ns ns ns ns ns ns ns ns ns ns
2584 tbl 70
-- 8
AR
12 13 11 11 9
11(6) 11
IN
Set-up Time Min. 3 2 5(15) 11 6 6 13 8 14 3
Enable Min. 0 0 Max. 7 7 Min. 0 0
u u u
11(6)
17(2)
SET-UP AND HOLD TIMES RELATIVE TO LATCH ENABLES
From Input DATA0-31 (4) CB0-7
(4)
IM
LEIN LEIN
DATA0-31 (4, 6) CB0-7 (CODE ID 00, 11) (4, 6) CB0-7 (CODE ID CORRECT(4, 6) DIAG MODE(4, 6) CODE ID1,0(4, 6) LEIN(4, 6) DATA0-31 (4, 6)
NOTE: (15) above applies to correction path.
EL
10)(4, 6)
d d d d d ud d d ud
To Input (Latching Data)
Y
7 7
u d
d u
d u
--
14 15 16 13 13 11
Hold Time Min. 3 3 0 0 0 0 0 0 0 3
Unit ns ns ns ns ns ns ns ns ns ns
2584 tbl 71
LEOUT/GENERATE LEOUT/GENERATE LEOUT/GENERATE LEOUT/GENERATE LEOUT/GENERATE LEOUT/GENERATE LEOUT/GENERATE LEDIAG
OUTPUT ENABLE/DISABLE TIMES(5)
PR
Disable Max. 6 6 Unit ns ns
2584 tbl 72
OE Byte0-3 OESC
From Input
Enable
d d
Disable
u u
To Output DATA0-31 SC0-7
MINIMUM PULSE WIDTHS
LEIN, LEOUT/GENERATE, LEDIAG
NOTES: 2584 tbl 73 1. CI = 50pF. 2. These parameters are combinational propagation delay calculations, and are not tested in production. 3. Data In or Correct Data Out measurement requires timing as shown in the Switching Waveforms. 4. Set-up and Hold times relative to Latch Enables (Latching Data). 5. Output tests specified with CI = 5pF and measured to 0.5V change of output level. Testing is performed at CI = 50pF and correlated to CI = 5pF. 6. Not production tested, guaranteed by characterization.
ud (Positive-going pulse)
Min. 5 ns
11.6
18
IDT49C460/A/B/C/D/E 32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT49C460D AC ELECTRICAL CHARACTERISTICS
(Guaranteed Commercial Range Performance) Temperature range: 0C to +70C, VCC = 5.0V 5% The inputs switch between 0V to 3V with signal measured at the 1.5V level.
PROPAGATION DELAYS(1)
To Output From Input DATA0-31 (3) CB0-7 (CODE ID1,0 = 00, 11) CB0-7 (CODE ID1,0 = 10) LEOUT/GENERATE CORRECT Not Internal Control Mode DIAG MODE Not Internal Control Mode CODE ID1,0 LEIN From latched to Transparent LEDIAG From latched to Transparent Internal Control Mode LEDIAG (Internal Control Mode) From latched to Transparent DATA0-31 (Internal Control Mode) Via Diagnostic Latch SC0-7 14 11 12 -- 14 -- 12 14(6) 17 DATA0-31 18(2) 16 12 9 -- 12 20 18 21 18 17 19(2)
ERROR
12 10 -- 7 7 -- 10 13 14 12 12 10
MULT ERROR
15 12 -- 8 8 -- 15 16 17 14 14 12
Unit ns ns ns ns ns ns ns ns ns ns ns ns
2584 tbl 28
u d
d u
d u
u u u
12(6) 12(6) 12
SET-UP AND HOLD TIMES RELATIVE TO LATCH ENABLES
From Input DATA0-31 (4) CB0-7
(4)
DATA0-31 (4, 6) CB0-7 (CODE ID 00, 11) (4, 6) CB0-7 (CODE ID 10)(4, 6) CORRECT(4, 6) DIAG MODE(4, 6) CODE ID1,0(4, 6) LEIN(4, 6) DATA0-31 (4, 6)
NOTE: (15) above applies to correction path.
d d d d d ud d d ud
To Input (Latching Data) LEIN LEIN LEOUT/GENERATE LEOUT/GENERATE LEOUT/GENERATE LEOUT/GENERATE LEOUT/GENERATE LEOUT/GENERATE LEOUT/GENERATE LEDIAG
Set-up Time Min. 3 2 5(15) 11 6 6 13 8 14 3
Hold Time Min. 3 3 0 0 0 0 0 0 0 3
Unit ns ns ns ns ns ns ns ns ns ns
2584 tbl 29
OUTPUT ENABLE/DISABLE TIMES(5)
Enable Disable Min. 0 0 Max. 10 10 From Input Enable
OE Byte0-3 OESC
d d
Disable
u u
To Output DATA0-31 SC0-7
Min. 0 0
Max. 8 8
Unit ns ns
2584 tbl 30
MINIMUM PULSE WIDTHS
LEIN, LEOUT/GENERATE, LEDIAG
(6)
NOTES: 2584 tbl 31 1. CI = 50pF. 2. These parameters are combinational propagation delay calculations, and are not tested in production. 3. Data In or Correct Data Out measurement requires timing as shown in the Switching Waveforms. 4. Set-up and Hold times relative to Latch Enables (Latching Data). 5. Output tests specified with CI = 5pF and measured to 0.5V change of output level. Testing is performed at CI = 50pF and correlated to CI = 5pF. 6. Not production tested, guaranteed by characterization.
ud (Positive-going pulse)
Min. 5 ns
11.6
19
IDT49C460/A/B/C/D/E 32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT49C460D AC ELECTRICAL CHARACTERISTICS
(Guaranteed Military Range Performance) Temperature range: -55C to +125C, VCC = 5.0V 10% The inputs switch between 0V to 3V with signal measured at the 1.5V level.
PROPAGATION DELAYS(1)
To Output From Input DATA0-3 (3) CB0-7 (CODE ID1,0 = 00, 11) CB0-7 (CODE ID1,0 = 10) LEOUT/GENERATE CORRECT Not Internal Control Mode DIAG MODE Not Internal Control Mode CODE ID1,0 LEIN From latched to Transparent LEDIAG From latched to Transparent Internal Control Mode LEDIAG From latched to Transparent DATA0-31 Via Diagnostic Latch SC0-7 17 13 13 -- 15 -- 14 16(6) 18 DATA0-31 22(2) 17 14 10 -- 13 22 20 24 20 19 22
(2)
ERROR
16 12 -- 8 8 -- 12 15 16 13 14 11
MULT ERROR
18 14 -- 8 9 -- 17 18 19 16 16 14
Unit ns ns ns ns ns ns ns ns ns ns ns ns
2584 tbl 32
u d
d u
d u
u u u
14(6) 14(6) 14
SET-UP AND HOLD TIMES RELATIVE TO LATCH ENABLES
From Input DATA0-31 (4) CB0-7(4) DATA0-31 (4, 6) CB0-7 (CODE ID 00, 11) (4, 6) CB0-7 (CODE ID CORRECT(4, 6) DIAG MODE(4, 6) CODE ID1,0(4, 6) LEIN(4, 6) DATA0-31 (4, 6)
NOTE: (15) above applies to correction path.
10)(4, 6)
d d d d d ud d d ud
To Input (Latching Data) LEIN LEIN LEOUT/GENERATE LEOUT/GENERATE LEOUT/GENERATE LEOUT/GENERATE LEOUT/GENERATE LEOUT/GENERATE LEOUT/GENERATE LEDIAG
Set-up Time Min. 3 2 6(15) 12 8 7 14 9 16 3
Hold Time Min. 3 3 0 0 0 0 0 0 0 3
Unit ns ns ns ns ns ns ns ns ns ns
2584 tbl 33
OUTPUT ENABLE/DISABLE TIMES(5)
Enable Disable Min. 0 0 Max. 12 12 Unit ns ns
2584 tbl 34
OE Byte0-3 OESC
From Input
Enable
d d
Disable
u u
To Output DATA0-31 SC0-7
Min. 0 0
Max. 10 10
MINIMUM PULSE WIDTHS
LEIN, LEOUT/GENERATE, LEDIAG
(6)
ud (Positive-going pulse)
Min. 5 ns
NOTES: 2584 tbl 35 1. CI = 50pF. 2. These parameters are combinational propagation delay calculations, and are not tested in production. 3. Data In or Correct Data Out measurement requires timing as shown in the Switching Waveforms. 4. Set-up and Hold times relative to Latch Enables (Latching Data). 5. Output tests specified with CI = 5pF and measured to 0.5V change of output level. Testing is performed at CI = 50pF and correlated to CI = 5F. 6. Not production tested, guaranteed by characterization.
11.6
20
IDT49C460/A/B/C/D/E 32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT49C460C AC ELECTRICAL CHARACTERISTICS
(Guaranteed Commercial Range Performance) Temperature range: 0C to +70C, VCC = 5.0V 5% The inputs switch between 0V to 3V with signal measured at the 1.5V level.
PROPAGATION DELAYS(1)
To Output From Input DATA0-31 (3) CB0-7 (CODE ID1,0 = 00, 11) CB0-7 (CODE ID1,0 = 10) LEOUT/GENERATE CORRECT Not Internal Control Mode DIAG MODE Not Internal Control Mode CODE ID1,0 LEIN From latched to Transparent LEDIAG From latched to Transparent Internal Control Mode LEDIAG From latched to Transparent DATA0-31 Via Diagnostic Latch SC0-7 19 14 14 -- 18 -- 16 18(6) 22 DATA0-31 24(2) 21 16 12 -- 16 26 23 28(2) 24 22 25(2)
ERROR
16 12 -- 9 9 -- 11 17 19 15 15 13
MULT ERROR
20 16 -- 11 11 -- 20 21 22 19 18 16
Unit ns ns ns ns ns ns ns ns ns ns ns ns
2584 tbl 36
u d
d u
d u
u u u
15(6) 16(6) 15
SET-UP AND HOLD TIMES RELATIVE TO LATCH ENABLES
From Input DATA0-31 (4) CB0-7(4) DATA0-31 (4, 6) CB0-7 (CODE ID 00, 11) (4, 6) CB0-7 (CODE ID 10)(4, 6) CORRECT(4, 6) DIAG MODE(4, 6) CODE ID1,0(4, 6) LEIN(4, 6) DATA0-31 (4, 6)
NOTE: (16) above applies to correction path.
d d d d d ud d d ud
To Input (Latching Data) LEIN LEIN LEOUT/GENERATE LEOUT/GENERATE LEOUT/GENERATE LEOUT/GENERATE LEOUT/GENERATE LEOUT/GENERATE LEOUT/GENERATE LEDIAG
Set-up Time Min. 3 2 6(16) 14 8 8 17 10 19 3
Hold Time Min. 4 4 0 0 0 0 0 0 0 3
Unit ns ns ns ns ns ns ns ns ns ns
2584 tbl 37
OUTPUT ENABLE/DISABLE TIMES(5)
Enable Disable Min. 0 0 Max. 12 12 Unit ns ns
2584 tbl 38
OE Byte0-3 OESC
From Input
Enable
d d
Disable
u u
To Output DATA0-31 SC0-7
Min. 0 0
Max. 10 10
MINIMUM PULSE WIDTHS
LEIN, LEOUT/GENERATE, LEDIAG
(6)
ud (Positive-going pulse)
Min. 6 ns
NOTES: 2584 tbl 39 1. CI = 50pF. 2. These parameters are combinational propagation delay calculations, and are not tested in production. 3. Data In or Correct Data Out measurement requires timing as shown in the Switching Waveforms. 4. Set-up and Hold times relative to Latch Enables (Latching Data). 5. Output tests specified with CI = 5pF and measured to 0.5V change of output level. Testing is performed at CI = 50pF and correlated to CI = 5pF. 6. Not production tested, guaranteed by characterization.
11.6
21
IDT49C460/A/B/C/D/E 32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT49C460C AC ELECTRICAL CHARACTERISTICS
(Guaranteed Military Range Performance) Temperature range: -55C to +125C, VCC = 5.0V 10% The inputs switch between 0V to 3V with signal measured at the 1.5V level.
PROPAGATION DELAYS(1)
To Output From Input DATA0-31 (3) CB0-7 (CODE ID1,0 = 00, 11) CB0-7 (CODE ID1,0 = 10) LEOUT/GENERATE CORRECT Not Internal Control Mode DIAG MODE Not Internal Control Mode CODE ID1,0 LEIN From latched to Transparent LEDIAG From latched to Transparent Internal Control Mode LEDIAG From latched to Transparent DATA0-31 Via Diagnostic Latch SC0-7 22 17 17 -- 20 -- 18 21
(6)
DATA0-31 29(2) 23 18 13 -- 17 29 26 32 27 25 29(2)
ERROR
21 16 -- 10 10 -- 12 20 21 17 18 14
MULT ERROR
24 18 -- 12 12 -- 23 24 25 21 21 18
Unit ns ns ns ns ns ns ns ns ns ns ns ns
2584 tbl 40
u d
d u
d u
24
u u u
18 19
(6)
(6)
18
SET-UP AND HOLD TIMES RELATIVE TO LATCH ENABLES
From Input DATA0-31 (4) CB0-7(4) DATA0-31 (4, 6) CB0-7 (CODE ID 00, 11) (4, 6) CB0-7 (CODE ID 10)(4, 6) CORRECT(4, 6) DIAG MODE(4, 6) CODE ID1,0(4, 6) LEIN(4, 6) DATA0-31 (4, 6)
Note: (19) above applies to correction path.
d d d d d ud d d ud
(5)
To Input (Latching Data) LEIN LEIN LEOUT/GENERATE LEOUT/GENERATE LEOUT/GENERATE LEOUT/GENERATE LEOUT/GENERATE LEOUT/GENERATE LEOUT/GENERATE LEDIAG
Set-up Time Min. 3 2 7(19) 16 10 9 19 12 21 3
Hold Time Min. 4 4 3 0 0 0 0 0 0 3
Unit ns ns ns ns ns ns ns ns ns ns
2584 tbl 41
OUTPUT ENABLE/DISABLE TIMES
Enable
Disable Min. 0 0
Min. 6 ns
OE Byte0-3 OESC
From Input
Enable
d d
Disable
u u
To Output DATA0-31 SC0-7
Min. 0 0
Max. 12 12
Max. 14 14
Unit ns ns
2584 tbl 42
MINIMUM PULSE WIDTHS(6)
LEIN, LEOUT/GENERATE, LEDIAG
ud (Positive-going pulse)
NOTES: 2584 tbl 43 1. CI = 50pF. 2. These parameters are combinational propagation delay calculations, and are not tested in production. 3. Data In or Correct Data Out measurement requires timing as shown in the Switching Waveforms. 4. Set-up and Hold times relative to Latch Enables (Latching Data). 5. Output tests specified with CI = 5pF and measured to 0.5V change of output level. Testing is performed at CI = 50pF and correlated to CI = 5F. 6. Not production tested, guaranteed by characterization. 11.6 22
IDT49C460/A/B/C/D/E 32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT49C460B AC ELECTRICAL CHARACTERISTICS
(Guaranteed Commercial Range Performance) Temperature range: 0C to +70C, VCC = 5.0V 5% The inputs switch between 0V to 3V with signal measured at the 1.5V level.
PROPAGATION DELAYS(1)
To Output From Input DATA0-31 (3) CB0-7 (CODE ID1,0 = 00, 11) CB0-7 (CODE ID1,0 = 10) LEOUT/GENERATE CORRECT Not Internal Control Mode DIAG MODE Not Internal Control Mode CODE ID1,0 LEIN From latched to Transparent LEDIAG From latched to Transparent Internal Control Mode LEDIAG From latched to Transparent DATA0-31 Via Diagnostic Latch SC0-7 25 14 16 -- 21 -- 17 18(6) 27 DATA0-31 30(2) 30 18 12 -- 23 26 26 38
(2)
ERROR
25 17 -- 23 23 -- 20 21 30 19 19 20
MULT ERROR
27 20 -- 23 23 -- 24 26 3 22 24 25
Unit ns ns ns ns ns ns ns ns ns ns ns ns
2584 tbl 44
u d
d u
d u
u u u
15(6) 16(6) 16
29 32 32
(2)
SET-UP AND HOLD TIMES RELATIVE TO LATCH ENABLES
From Input DATA0-31 (4) CB0-7(4) DATA0-31 (4, 6) CB0-7 (CODE ID 00, 11) (4, 6) CB0-7 (CODE ID CORRECT(4, 6) DIAG MODE(4, 6) CODE ID1,0(4, 6) LEIN(4, 6) DATA0-31 (4, 6) 10)(4, 6)
d d d d d ud d d ud
(5)
To Input (Latching Data) LEIN LEIN LEOUT/GENERATE LEOUT/GENERATE LEOUT/GENERATE LEOUT/GENERATE LEOUT/GENERATE LEOUT/GENERATE LEOUT/GENERATE LEDIAG
Set-up Time Min. 4 4 19 15 15 11 17 17 20 4
Hold Time Min. 4 4 0 0 0 0 0 0 0 3
Unit ns ns ns ns ns ns ns ns ns ns
2584 tbl 45
OUTPUT ENABLE/DISABLE TIMES
Enable
Disable Min. 0 0
Min. 9 ns
OE Byte0-3 OESC
From Input
Enable
d d
Disable
u u
To Output DATA0-31 SC0-7
Min. 0 0
Max. 12 12
Max. 14 14
Unit ns ns
2584 tbl 46
MINIMUM PULSE WIDTHS
LEIN, LEOUT/GENERATE, LEDIAG
ud (Positive-going pulse)
NOTES: 2584 tbl 47 1. CI = 50pF. 2. These parameters are combinational propagation delay calculations, and are not tested in production. 3. Data In or Correct Data Out measurement requires timing as shown in the Switching Waveforms. 4. Set-up and Hold times relative to Latch Enables (Latching Data). 5. Output tests specified with CI = 5pF and measured to 0.5V change of output level. Testing is performed at CI = 50pF and correlated to CI = 5pF. 6. Not production tested, guaranteed by characterization.
11.6
23
IDT49C460/A/B/C/D/E 32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT49C460B AC ELECTRICAL CHARACTERISTICS
(Guaranteed Military Range Performance) Temperature range: -55C to +125C, VCC = 5.0V 10% The inputs switch between 0V to 3V with signal measured at the 1.5V level.
PROPAGATION DELAYS(1)
To Output From Input DATA0-31 (3) CB0-7 (CODE ID1,0 = 00, 11) CB0-7 (CODE ID1,0 = 10) LEOUT/GENERATE CORRECT Not Internal Control Mode DIAG MODE Not Internal Control Mode CODE ID1,0 LEIN From latched to Transparent LEDIAG From latched to Transparent Internal Control Mode LEDIAG From latched to Transparent DATA0-31 Via Diagnostic Latch SC0-7 28 17 19 -- 24 -- 20 21 30 DATA0-31 33(2) 33 23 15 -- 26 29 29 41 32 35 35(2)
ERROR
28 20 -- 26 26 -- 23 24 33 22 22 23
MULT ERROR
30 23 -- 26 26 -- 27 29 36 25 27 28
Unit ns ns ns ns ns ns ns ns ns ns ns ns
2584 tbl 48
u d
d u
d u
u u u
18 19 19
SET-UP AND HOLD TIMES RELATIVE TO LATCH ENABLES
From Input DATA0-31 (4) CB0-7
(4)
DATA0-31 (4, 6) CB0-7 (CODE ID 00, 11) (4, 6) CB0-7 (CODE ID 10)(4, 6) CORRECT(4, 6) DIAG MODE(4, 6) CODE ID1,0(4, 6) LEIN(4, 6) DATA0-31 (4, 6)
d d d d d ud d d ud
To Input (Latching Data) LEIN LEIN LEOUT/GENERATE LEOUT/GENERATE LEOUT/GENERATE LEOUT/GENERATE LEOUT/GENERATE LEOUT/GENERATE LEOUT/GENERATE LEDIAG
Set-up Time Min. 4 4 23 18 18 14 20 20 23 4
Hold Time Min. 4 4 0 0 0 0 0 0 0 3
Unit ns ns ns ns ns ns ns ns ns ns
2584 tbl 49
OUTPUT ENABLE/DISABLE TIMES(5)
Enable Disable Min. 0 0 Max. 14 14 Unit ns ns
2584 tbl 50
OE Byte0-3 OESC
From Input
Enable
d d
Disable
u u
To Output DATA0-31 SC0-7
Min. 0 0
Max. 12 12
MINIMUM PULSE WIDTHS
LEIN, LEOUT/GENERATE, LEDIAG
ud (Positive-going pulse)
Min. 12 ns
NOTES: 2584 tbl 51 1. CI = 50pF. 2. These parameters are combinational propagation delay calculations, and are not tested in production. 3. Data In or Correct Data Out measurement requires timing as shown in the Switching Waveforms. 4. Set-up and Hold times relative to Latch Enables (Latching Data). 5. Output tests specified with CI = 5pF and measured to 0.5V change of output level. Testing is performed at CI = 50pF and correlated to CI = 5pF. 6. Not production tested, guaranteed by characterization.
11.6
24
IDT49C460/A/B/C/D/E 32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT49C460A AC ELECTRICAL CHARACTERISTICS
(Guaranteed Commercial Range Performance) Temperature range: 0C to 70C, VCC = 5.0V 5% The inputs switch between 0V to 3V with signal measured at the 1.5V level.
PROPAGATION DELAYS(1)
To Output From Input DATA0-31 (3) CB0-7 (CODE ID1,0 = 00, 11) CB0-7 (CODE ID1,0 = 10) LEOUT/GENERATE CORRECT Not Internal Control Mode DIAG MODE Not Internal Control Mode CODE ID1,0 LEIN From latched to Transparent LEDIAG From latched to Transparent Internal Control Mode LEDIAG From latched to Transparent DATA0-31 Via Diagnostic Latch SC0-7 27 16 16 -- 21 -- 17 18 27 DATA0-31 36(2) 34 20 12 -- 23 26 26 38 29 32 32(2)
ERROR
30 19 -- 25 25 -- 20 21 30 19 29 20
MULT ERROR
33 23 -- 25 25 -- 24 26 33 22 24 25
Unit ns ns ns ns ns ns ns ns ns ns ns ns
2584 tbl 52
u d
d u
d u
u u u
15 16 16
SET-UP AND HOLD TIMES RELATIVE TO LATCH ENABLES
From Input DATA0-31 (4) CB0-7(4) DATA0-31 (4, 6) CB0-7 (CODE ID 00, CORRECT(4, 6) DIAG MODE(4, 6) CODE ID1,0(4, 6) LEIN(4, 6) DATA0-31 (4, 6) 11) (4, 6) CB0-7 (CODE ID 10)(4, 6)
d d d d d ud d d ud
(5)
To Input (Latching Data) LEIN LEIN LEOUT/GENERATE LEOUT/GENERATE LEOUT/GENERATE LEOUT/GENERATE LEOUT/GENERATE LEOUT/GENERATE LEOUT/GENERATE LEDIAG
Set-up Time Min. 5 5 23 15 15 11 17 17 25 5
Hold Time Min. 4 4 0 0 0 0 0 0 0 3
Unit ns ns ns ns ns ns ns ns ns ns
2584 tbl 53
OUTPUT ENABLE/DISABLE TIMES
Enable
Disable Min. 0 0
Min. 9 ns
OE Byte0-3 OESC
From Input
Enable
d d
Disable
u u
To Output DATA0-31 SC0-7
Min. 0 0
Max. 12 12
Max. 14 14
Unit ns ns
2584 tbl 54
MINIMUM PULSE WIDTHS
LEIN, LEOUT/GENERATE, LEDIAG
ud (Positive-going pulse)
NOTES: 2584 tbl 55 1. CI = 50pF. 2. These parameters are combinational propagation delay calculations, and are not tested in production. 3. Data In or Correct Data Out measurement requires timing as shown in the Switching Waveforms. 4. Set-up and Hold times relative to Latch Enables (Latching Data). 5. Output tests specified with CI = 5pF and measured to 0.5V change of output level. Testing is performed at CI = 50pF and correlated to CI = 5pF. 6. Not production tested, guaranteed by characterization.
11.6
25
IDT49C460/A/B/C/D/E 32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT49C460A AC ELECTRICAL CHARACTERISTICS
(Guaranteed Military Range Performance) Temperature range: -55C to +125C, VCC = 5.0V 10% The inputs switch between 0V to 3V with signal measured at the 1.5V level.
PROPAGATION DELAYS(1)
To Output From Input DATA0-31 (3) CB0-7 (CODE ID1,0 = 00, 11) CB0-7 (CODE ID1,0 = 10) LEOUT/GENERATE CORRECT Not Internal Control Mode DIAG MODE Not Internal Control Mode CODE ID1,0 LEIN From latched to Transparent LEDIAG From latched to Transparent Internal Control Mode LEDIAG From latched to Transparent DATA0-31 Via Diagnostic Latch SC0-7 30 19 19 -- 24 -- 20 21 30 DATA0-31 39(2) 37 23 15 -- 26 29 29 41 32 35 35(2)
ERROR
33 22 -- 28 28 -- 23 24 33 22 22 23
MULT ERROR
36 26 -- 28 28 -- 27 29 36 25 27 28
Unit ns ns ns ns ns ns ns ns ns ns ns ns
2584 tbl 56
u d
d u
d u
u u u
18 19 19
SET-UP AND HOLD TIMES RELATIVE TO LATCH ENABLES
From Input DATA0-3 (4) CB0-7(4) DATA0-31 (4, 6) CB0-7 (CODE ID 00, 11) (4, 6) CB0-7 (CODE ID CORRECT(4, 6) DIAG MODE(4, 6) CODE ID1,0(4, 6) LEIN(4, 6) DATA0-31 (4, 6) 10)(4, 6)
d d d d d ud d d ud
To Input (Latching Data) LEIN LEIN LEOUT/GENERATE LEOUT/GENERATE LEOUT/GENERATE LEOUT/GENERATE LEOUT/GENERATE LEOUT/GENERATE LEOUT/GENERATE LEDIAG
Set-up Time Min. 5 5 27 18 18 14 20 20 28 5
Hold Time Min. 4 4 0 0 0 0 0 0 0 3
Unit ns ns ns ns ns ns ns ns ns ns
2584 tbl 57
OUTPUT ENABLE/DISABLE TIMES(5)
Enable Disable Min. 0 0
Min. 12 ns
OE Byte0-3 OESC
From Input
Enable
d d
Disable
u u
To Output DATA0-31 SC0-7
Min. 0 0
Max. 12 12
Max. 14 14
Unit ns ns
2584 tbl 58
MINIMUM PULSE WIDTHS
LEIN, LEOUT/GENERATE, LEDIAG
ud (Positive-going pulse)
NOTES: 2584 tbl 59 1. CI = 50pF. 2. These parameters are combinational propagation delay calculations, and are not tested in production. 3. Data In or Correct Data Out measurement requires timing as shown in the Switching Waveforms. 4. Set-up and Hold times relative to Latch Enables (Latching Data). 5. Output tests specified with CI = 5pF and measured to 0.5V change of output level. Testing is performed at CI = 50pF and correlated to CI = 5pF. 6. Not production tested, guaranteed by characterization.
11.6
26
IDT49C460/A/B/C/D/E 32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT49C460 AC ELECTRICAL CHARACTERISTICS
(Guaranteed Commercial Range Performance) Temperature range: 0C to +70C, VCC = 5.0V 5% The inputs switch between 0V to 3V with signal measured at the 1.5V level.
PROPAGATION DELAYS(1)
To Output From Input DATA0-31 (3) CB0-7 (CODE ID1,0 = 00, 11) CB0-7 (CODE ID1,0 = 10) LEOUT/GENERATE CORRECT Not Internal Control Mode DIAG MODE Not Internal Control Mode CODE ID1,0 LEIN From latched to Transparent LEDIAG From latched to Transparent Internal Control Mode LEDIAG From latched to Transparent DATA0-31 Via Diagnostic Latch SC0-7 37 22 22 -- 29 -- 23 25 37 DATA0-31 49(2) 46 30 17 -- 31 35 35 51 38 42 42(2)
ERROR
40 26 -- 30 30 -- 27 29 41 26 26 27
MULT ERROR
45 31 -- 30 30 -- 33 35 45 30 33 34
Unit ns ns ns ns ns ns ns ns ns ns ns ns
2584 tbl 60
u d
d u
d u
u u u
21 22 22
SET-UP AND HOLD TIMES RELATIVE TO LATCH ENABLES
From Input DATA0-31 (4) CB0-7(4) DATA0-31 (4, 6) CB0-7 (CODE ID 00, 11) (4, 6) CB0-7 (CODE ID CORRECT(4, 6) DIAG LEIN MODE(4, 6)
(4, 6) (4, 6)
10)(4, 6)
CODE ID1,0(4, 6) DATA0-31
d d d d d ud d d ud
To Input (Latching Data) LEIN LEIN LEOUT/GENERATE LEOUT/GENERATE LEOUT/GENERATE LEOUT/GENERATE LEOUT/GENERATE LEOUT/GENERATE LEOUT/GENERATE LEDIAG
Set-up Time Min. 6 5 30 20 20 16 23 23 31 6
Hold Time Min. 4 4 0 0 0 0 0 0 0 3
Unit ns ns ns ns ns ns ns ns ns ns
2584 tbl 61
OUTPUT ENABLE/DISABLE TIMES(5)
Enable Disable Min. 0 0 Max. 17 17 Unit ns ns
2584 tbl 62
OE Byte0-3 OESC
From Input
Enable
d d
Disable
u u
To Output DATA0-31 SC0-7
Min. 0 0
Max. 15 15
MINIMUM PULSE WIDTHS
LEIN, LEOUT/GENERATE, LEDIAG
NOTES: 2584 tbl 63 1. CI = 50pF. 2. These parameters are combinational propagation delay calculations, and are not tested in production. 3. Data In or Correct Data Out measurement requires timing as shown in the Switching Waveforms. 4. Set-up and Hold times relative to Latch Enables (Latching Data). 5. Output tests specified with CI = 5pF and measured to 0.5V change of output level. Testing is performed at CI = 50pF and correlated to CI = 5pF. 6. Not production tested, guaranteed by characterization.
ud (Positive-going pulse)
Min. 12 ns
11.6
27
IDT49C460/A/B/C/D/E 32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT49C460 AC ELECTRICAL CHARACTERISTICS
(Guaranteed Military Range Performance) Temperature range: -55C to +125C, VCC = 5.0V 10% The inputs switch between 0V to 3V with signal measured at the 1.5V level.
PROPAGATION DELAYS(1)
To Output From Input DATA0-31 (3) CB0-7 (CODE ID1,0 = 00, 11) CB0-7 (CODE ID1,0 = 10) LEOUT/GENERATE CORRECT Not Internal Control Mode DIAG MODE Not Internal Control Mode CODE ID1,0 LEIN From latched to Transparent LEDIAG From latched to Transparent Internal Control Mode LEDIAG From latched to Transparent DATA0-31 Via Diagnostic Latch SC0-7 40 25 25 -- 32 -- 26 28 40 DATA0-31 52(2) 49 33 20 -- 34 38 38 54 42 47(2) 47
ERROR
44 29 -- 33 33 -- 30 32 44 29 29 30
MULT ERROR
48 34 -- 33 33 -- 36 38 48 33 36 37
Unit ns ns ns ns ns ns ns ns ns ns ns ns
2584 tbl 64
u d
d u
d u
u u u
24 25 25
SET-UP AND HOLD TIMES RELATIVE TO LATCH ENABLES
From Input DATA0-31 (4) CB0-7(4) DATA0-31 (4, 6) CB0-7 (CODE ID 00, 11) (4, 6) CB0-7 (CODE ID 10)(4, 6) CORRECT(4, 6) DIAG MODE(4, 6) CODE ID1,0(4, 6) LEIN(4, 6) DATA0-31 (4, 6)
d d d d d ud d d ud
To Input (Latching Data) LEIN LEIN LEOUT/GENERATE LEOUT/GENERATE LEOUT/GENERATE LEOUT/GENERATE LEOUT/GENERATE LEOUT/GENERATE LEOUT/GENERATE LEDIAG
Set-up Time Min. 6 5 36 24 24 20 28 28 37 6
Hold Time Min. 4 4 0 0 0 0 0 0 0 3
Unit ns ns ns ns ns ns ns ns ns ns
2584 tbl 65
OUTPUT ENABLE/DISABLE TIMES(5)
Enable Disable Min. 0 0
Min. (Positive-going pulse) 15
OE Byte0-3 OESC
From Input
Enable
d d
Disable
u
To Output DATA0-31 SC0-7
Min. 0 0
Max. 15 15
Max. 17 17
Unit ns ns
2584 tbl 66
MINIMUM PULSE WIDTHS
LEIN, LEOUT/GENERATE, LEDIAG
ns
NOTES: 2584 tbl 67 1. CI = 5pF. 2. These parameters are combinational propagation delay calculations, and are not tested in production. 3. Data In or Correct Data Out measurement requires timing as shown in the Switching Waveforms. 4. Set-up and Hold times relative to Latch Enables (Latching Data). 5. Output tests specified with CI = 5pF and measured to 0.5V change of output level. Testing is performed at CI = 50pF and correlated to CI = 5pF. 6. Not production tested, guaranteed by characterization.
11.6
28
IDT49C460/A/B/C/D/E 32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DETECT OR CORRECTION MODE (FROM GENERATE MODE)
Propagation Delay From To Min./Max.
OE byte
0 6 7 0
OE byte = High to DATAOUT Disabled OE byte = High to DATAOUT Disabled OE byte = Low to DATAOUT Enabled OE byte = Low to DATAOUT Enabled
OUT
Min. Max. Min. Max.
DATA bus
(Output)
Valid DATA IN 14
(Corrected DATA if Correct Mode) (DATAIN if Detect Mode) DATAIN to DATAOUT
Max.
CBIN
Valid Checkbits In 11
CORRECT = High to DATAOUT
Max.
CORRECT
CODE ID1,0 = 00, 11 CODE ID1,0 = 10 19* 12 10
CBIN to DATAOUT CBIN to DATAOUT *LEIN = High to DATAOUT
Max. Max. Max.
LEIN. LEOUT/GEN
9 8 7 10 7 13*
ERROR
11 9 16*
LEOUT/GEN = High to DATAOUT LEOUT/GEN = High to MERROR = Low LEOUT/GEN = High to ERROR = Low DATAIN to ERROR = Low CBIN to ERROR = Low *LEIN = High to ERROR = Low* (Low = Error) DATAIN to MERROR = Low CBIN to MERROR = Low *LEIN = High to MERROR = Low* (Low = Error) DATAIN to SCOUT CBIN to SCOUT
Max. Max. Max. Max. Max. Max.
MERROR
Max. Max. Max.
11 9
Max. Max.
OESC
0 6 0 7 Valid
OESC = High to SCOUT Disabled OESC = High to SCOUT Disabled OESC = Low to SCOUT Enabled OESC = Low to SCOUT Enabled
(Syndrome Bits Come Out)
Min. Max. Min. Max.
SCOUT
NOTES: 1. BOLD indicates critical parameters. 2. This is "E" version timing spec. Check appropriate table for other speed versions. * Assumes "CBIN" and/or "DATAIN" are valid at least 4ns before "LEIN" goes high.
2584 drw 10
11.6
29
IDT49C460/A/B/C/D/E 32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
GENERATE MODE (FROM DETECT OR CORRECTION MODE)
Propagation Delay From To Min./Max.
OE byte
0 6 0 7
OE byte = High to DATAOUT Disabled OE byte = High to DATAOUT Disabled OE byte = Low to DATAOUT Enabled OE byte = Low to DATAOUT Enabled
OUT
Min. Max. Min. Max.
DATA Bus
(Output) CODE ID 1,0 = 10
Valid DATA IN 10 Valid Checkbits In
CBIN to DATAOUT
Max.
CBIN
LEIN
LEOUT/GEN
(Generate Mode) 7 13 11 16* 9
ERROR = High
LEOUT/GENERATE = Low to
Max. Max. Max. Max. Max.
ERR/MERR OESC
(CODE ID 1,0 = 10)
LEOUT/GENERATE = Low to SCOUT DATAIN to SCOUT *LEIN = High to SCOUT* CBIN to SCOUT (Forced High)
0 6 7 0
OESC = High to SCOUT Disabled OESC = High to SCOUT Disabled OESC = Low to SCOUT Enabled OESC = Low to SCOUT Enabled
Valid Checkbits
Min. Max. Min. Max.
SCOUT
(Check Bits Exit)
CORRECT
(Don't Care)
2584 drw 09
NOTES: 1. BOLD indicates critical parameters. 2. Valiid "DATA" and valid CBIN" are shown to occur simultaneously, since both buses are latched and opened by the "LEIN" input. 3. This is "E" version timing spec. Check appropriate table for other speed versions. * Assumes DATA bus becomes input 4ns before LEIN goes high.
11.6
30
IDT49C460/A/B/C/D/E 32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SET-UP AND HOLD TIMES AND MINIMUM PULSE WIDTHS
Of CBIN
2 3 Valid
Set-up/Hold Time With Respect To
Min./Max.
CBIN Set-up to LEIN = Low CBIN Hold to LEIN = Low LEIN width
Min. Min. Min. Min. Min. Min.
LEIN.
5 14* 3 3
*LEIN = High to LEOUT/GEN = Low* DATA Set-up to LEIN = Low DATA Hold to LEIN = Low
DATAIN
CODE ID1,0 = 00, 11 CODE ID1,0 = 10
Valid 11 6 6 5 6
CBIN Set-up to LEOUT/GEN = Low CBIN Set-up to LEOUT/GEN = Low DATA Set-up to LEOUT/GEN = Low LEOUT/GENERATE Width CORRECT Set-up to LEOUT/GEN = Low
Min. Min. Min. Min. Min.
LEOUT/GEN
CORRECT
NOTES: 2584 drw 11 1. BOLD indicates critical parameters. 2. This is "E" version timing spec. Check appropriate table for other speed versions. * Enable to enable timing requirement to ensure that the last DATA word applied to "DATAIN" is made available as DATAOUT"; assumes that "DATAIN" is valid at least 4ns before "LEIN" goes high.
INPUT/OUTPUT INTERFACE CIRCUIT
VCC
ESD PROTECTION IIH INPUTS IIL
IOH OUTPUTS IOL
2584 drw 12
2584 drw 13
Figure 5. Input Structure (All Inputs) Figure 6. Out put Structure
11.6
31
IDT49C460/A/B/C/D/E 32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TEST LOAD CIRCUIT
VCC
+ 7.0V
500 VIN Pulse Generator RT D.U.T. 50pF CL 500 VOUT
2584 drw 14
DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance RL = Termination resistance: should be equal to ZOUT of the Pulse Generator Figure 7.
AC TEST CONDITIONS
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load GND to 3.0V 1V/ns 1.5V 1.5V See Figure 7
2584 tbl 69
Test Disable Low Enable Low All other Tests
Switch Closed Open
2584 tbl 68
ORDERING INFORMATION
IDT 49C460 Device Type X Speed X Package X Process/ Temperature Range BLANK B Commercial (0C to + 70C) Military (- 55C to + 125C) Compliant to MIL-STD-883, Class B Pin Grid Array Plastic Leaded Chip Carrier Fine Pitch Flatpack Standard Speed High-Speed Very High-Speed Super-High-Speed Ultra-High Speed Fastest Speed
G J FF Blank A B C D E
49C460
32-Bit E. D. C.
2584 drw 15
11.6
32

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